Integrated circuit chips are often provided with low power modes where some or all of the chip can be powered down in order to reduce power consumption and reduce the amount of heat generated by the chip. These modes are referred to as sleep, standby, low power, and by a variety of other names. Multiple core chips may be able to slow down or turn off some cores while other cores continue to operate. For a more complex chip there may be many different sections within a single core that can be switched to a lower voltage or switched to standby. In order to change the power conditions for a section, there is a power gate for the section that controls the power supply. The power gate is operated by a power control section, an instruction manager or software. The control section determines whether a particular section is needed and, if not, then turns it off.
Standard power gating uses a single large switching device providing virtual power to a large section of the logic. The device is switched off during sleep times. During operation, it is switched back on and provides maximum power very quickly. The power must be close to Vcc (for a PMOS (P-type Metal Oxide Semiconductor) switch) or Vss (for an NMOS (N-type Metal Oxide Semiconductor) switch) during operation in order to all of the logic switches to function properly. The single switching device provides power to many different switching sections which present different loads at different times as the different sections are more or less used for the operations. In order to sustain and prevent voltage droops caused by the changing load, the power switches are made large. The interconnect lines between the power switching device and all of the loads are also made large.